rcar_gen3: drivers: pfc: Synchronize tables

Synchronize the pin control tables with Renesas ATF release 2.0.0 .

Signed-off-by: Marek Vasut <[email protected]>

diff --git a/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c b/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
index 47fa837b3ff070f0697d8ad19d2bfabf4e12389b..1fc13deae76e404810f96ffde47329e42563ff8b 100644 (file)
--- a/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
+++ b/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
@@ -490,7 +490,8 @@ void pfc_init_e3(void)
                      | MOD_SEL0_REMOCON_A
                      | MOD_SEL0_SCIF_A
                      | MOD_SEL0_SCIF0_A
-                     | MOD_SEL0_SCIF2_A | MOD_SEL0_SPEED_PULSE_IF_A);
+                     | MOD_SEL0_SCIF2_A
+                     | MOD_SEL0_SPEED_PULSE_IF_A);
        pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_SIMCARD_A
                      | MOD_SEL1_SSI2_A
                      | MOD_SEL1_TIMER_TMU_A
@@ -507,135 +508,137 @@ void pfc_init_e3(void)
                      | MOD_SEL1_SCIF4_A
                      | MOD_SEL1_SCIF5_A
                      | MOD_SEL1_VIN4_A
-                     | MOD_SEL1_VIN5_A | MOD_SEL1_ADGC_A | MOD_SEL1_SSI9_A);
+                     | MOD_SEL1_VIN5_A
+                     | MOD_SEL1_ADGC_A
+                     | MOD_SEL1_SSI9_A);
 
        /* initialize peripheral function select */
        pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)        /* QSPI1_MISO/IO1 */
-                     |IPSR_24_FUNC(0)  /* QSPI1_MOSI/IO0 */
-                     |IPSR_20_FUNC(0)  /* QSPI1_SPCLK */
-                     |IPSR_16_FUNC(0)  /* QSPI0_IO3 */
-                     |IPSR_12_FUNC(0)  /* QSPI0_IO2 */
-                     |IPSR_8_FUNC(0)   /* QSPI0_MISO/IO1 */
-                     |IPSR_4_FUNC(0)   /* QSPI0_MOSI/IO0 */
-                     |IPSR_0_FUNC(0)); /* QSPI0_SPCLK */
+                     | IPSR_24_FUNC(0) /* QSPI1_MOSI/IO0 */
+                     | IPSR_20_FUNC(0) /* QSPI1_SPCLK */
+                     | IPSR_16_FUNC(0) /* QSPI0_IO3 */
+                     | IPSR_12_FUNC(0) /* QSPI0_IO2 */
+                     | IPSR_8_FUNC(0)  /* QSPI0_MISO/IO1 */
+                     | IPSR_4_FUNC(0)  /* QSPI0_MOSI/IO0 */
+                     | IPSR_0_FUNC(0));        /* QSPI0_SPCLK */
        pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0)        /* AVB_RD2 */
-                     |IPSR_24_FUNC(0)  /* AVB_RD1 */
-                     |IPSR_20_FUNC(0)  /* AVB_RD0 */
-                     |IPSR_16_FUNC(0)  /* RPC_RESET# */
-                     |IPSR_12_FUNC(0)  /* RPC_INT# */
-                     |IPSR_8_FUNC(0)   /* QSPI1_SSL */
-                     |IPSR_4_FUNC(0)   /* QSPI1_IO3 */
-                     |IPSR_0_FUNC(0)); /* QSPI1_IO2 */
+                     | IPSR_24_FUNC(0) /* AVB_RD1 */
+                     | IPSR_20_FUNC(0) /* AVB_RD0 */
+                     | IPSR_16_FUNC(0) /* RPC_RESET# */
+                     | IPSR_12_FUNC(0) /* RPC_INT# */
+                     | IPSR_8_FUNC(0)  /* QSPI1_SSL */
+                     | IPSR_4_FUNC(0)  /* QSPI1_IO3 */
+                     | IPSR_0_FUNC(0));        /* QSPI1_IO2 */
        pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(1)        /* IRQ0 */
-                     |IPSR_24_FUNC(0)
+                     | IPSR_24_FUNC(0)
                      | IPSR_20_FUNC(0)
                      | IPSR_16_FUNC(2) /* AVB_LINK */
-                     |IPSR_12_FUNC(0)
+                     | IPSR_12_FUNC(0)
                      | IPSR_8_FUNC(0)  /* AVB_MDC */
-                     |IPSR_4_FUNC(0)   /* AVB_MDIO */
-                     |IPSR_0_FUNC(0)); /* AVB_TXCREFCLK */
+                     | IPSR_4_FUNC(0)  /* AVB_MDIO */
+                     | IPSR_0_FUNC(0));        /* AVB_TXCREFCLK */
        pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(5)        /* DU_HSYNC */
-                     |IPSR_24_FUNC(0)
+                     | IPSR_24_FUNC(0)
                      | IPSR_20_FUNC(0)
                      | IPSR_16_FUNC(0)
                      | IPSR_12_FUNC(5) /* DU_DG4 */
-                     |IPSR_8_FUNC(5)   /* DU_DOTCLKOUT0 */
-                     |IPSR_4_FUNC(5)   /* DU_DISP */
-                     |IPSR_0_FUNC(1)); /* IRQ1 */
+                     | IPSR_8_FUNC(5)  /* DU_DOTCLKOUT0 */
+                     | IPSR_4_FUNC(5)  /* DU_DISP */
+                     | IPSR_0_FUNC(1));        /* IRQ1 */
        pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(5)        /* DU_DB5 */
-                     |IPSR_24_FUNC(5)  /* DU_DB4 */
-                     |IPSR_20_FUNC(5)  /* DU_DB3 */
-                     |IPSR_16_FUNC(5)  /* DU_DB2 */
-                     |IPSR_12_FUNC(5)  /* DU_DG6 */
-                     |IPSR_8_FUNC(5)   /* DU_VSYNC */
-                     |IPSR_4_FUNC(5)   /* DU_DG5 */
-                     |IPSR_0_FUNC(5)); /* DU_DG7 */
+                     | IPSR_24_FUNC(5) /* DU_DB4 */
+                     | IPSR_20_FUNC(5) /* DU_DB3 */
+                     | IPSR_16_FUNC(5) /* DU_DB2 */
+                     | IPSR_12_FUNC(5) /* DU_DG6 */
+                     | IPSR_8_FUNC(5)  /* DU_VSYNC */
+                     | IPSR_4_FUNC(5)  /* DU_DG5 */
+                     | IPSR_0_FUNC(5));        /* DU_DG7 */
        pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(5)        /* DU_DR3 */
-                     |IPSR_24_FUNC(5)  /* DU_DB7 */
-                     |IPSR_20_FUNC(5)  /* DU_DR2 */
-                     |IPSR_16_FUNC(5)  /* DU_DR1 */
-                     |IPSR_12_FUNC(5)  /* DU_DR0 */
-                     |IPSR_8_FUNC(5)   /* DU_DB1 */
-                     |IPSR_4_FUNC(5)   /* DU_DB0 */
-                     |IPSR_0_FUNC(5)); /* DU_DB6 */
+                     | IPSR_24_FUNC(5) /* DU_DB7 */
+                     | IPSR_20_FUNC(5) /* DU_DR2 */
+                     | IPSR_16_FUNC(5) /* DU_DR1 */
+                     | IPSR_12_FUNC(5) /* DU_DR0 */
+                     | IPSR_8_FUNC(5)  /* DU_DB1 */
+                     | IPSR_4_FUNC(5)  /* DU_DB0 */
+                     | IPSR_0_FUNC(5));        /* DU_DB6 */
        pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(5)        /* DU_DG1 */
-                     |IPSR_24_FUNC(5)  /* DU_DG0 */
-                     |IPSR_20_FUNC(5)  /* DU_DR7 */
-                     |IPSR_16_FUNC(2)  /* IRQ5 */
-                     |IPSR_12_FUNC(5)  /* DU_DR6 */
-                     |IPSR_8_FUNC(5)   /* DU_DR5 */
-                     |IPSR_4_FUNC(0)
+                     | IPSR_24_FUNC(5) /* DU_DG0 */
+                     | IPSR_20_FUNC(5) /* DU_DR7 */
+                     | IPSR_16_FUNC(2) /* IRQ5 */
+                     | IPSR_12_FUNC(5) /* DU_DR6 */
+                     | IPSR_8_FUNC(5)  /* DU_DR5 */
+                     | IPSR_4_FUNC(0)
                      | IPSR_0_FUNC(5));        /* DU_DR4 */
        pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)        /* SD0_CLK */
-                     |IPSR_24_FUNC(0)
+                     | IPSR_24_FUNC(0)
                      | IPSR_20_FUNC(5) /* DU_DOTCLKIN0 */
-                     |IPSR_16_FUNC(5)  /* DU_DG3 */
-                     |IPSR_12_FUNC(0)
+                     | IPSR_16_FUNC(5) /* DU_DG3 */
+                     | IPSR_12_FUNC(0)
                      | IPSR_8_FUNC(0)
                      | IPSR_4_FUNC(0)
                      | IPSR_0_FUNC(5));        /* DU_DG2 */
        pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0)        /* SD1_DAT0 */
-                     |IPSR_24_FUNC(0)  /* SD1_CMD */
-                     |IPSR_20_FUNC(0)  /* SD1_CLK */
-                     |IPSR_16_FUNC(0)  /* SD0_DAT3 */
-                     |IPSR_12_FUNC(0)  /* SD0_DAT2 */
-                     |IPSR_8_FUNC(0)   /* SD0_DAT1 */
-                     |IPSR_4_FUNC(0)   /* SD0_DAT0 */
-                     |IPSR_0_FUNC(0)); /* SD0_CMD */
+                     | IPSR_24_FUNC(0) /* SD1_CMD */
+                     | IPSR_20_FUNC(0) /* SD1_CLK */
+                     | IPSR_16_FUNC(0) /* SD0_DAT3 */
+                     | IPSR_12_FUNC(0) /* SD0_DAT2 */
+                     | IPSR_8_FUNC(0)  /* SD0_DAT1 */
+                     | IPSR_4_FUNC(0)  /* SD0_DAT0 */
+                     | IPSR_0_FUNC(0));        /* SD0_CMD */
        pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)        /* SD3_DAT2 */
-                     |IPSR_24_FUNC(0)  /* SD3_DAT1 */
-                     |IPSR_20_FUNC(0)  /* SD3_DAT0 */
-                     |IPSR_16_FUNC(0)  /* SD3_CMD */
-                     |IPSR_12_FUNC(0)  /* SD3_CLK */
-                     |IPSR_8_FUNC(0)   /* SD1_DAT3 */
-                     |IPSR_4_FUNC(0)   /* SD1_DAT2 */
-                     |IPSR_0_FUNC(0)); /* SD1_DAT1 */
+                     | IPSR_24_FUNC(0) /* SD3_DAT1 */
+                     | IPSR_20_FUNC(0) /* SD3_DAT0 */
+                     | IPSR_16_FUNC(0) /* SD3_CMD */
+                     | IPSR_12_FUNC(0) /* SD3_CLK */
+                     | IPSR_8_FUNC(0)  /* SD1_DAT3 */
+                     | IPSR_4_FUNC(0)  /* SD1_DAT2 */
+                     | IPSR_0_FUNC(0));        /* SD1_DAT1 */
        pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0)       /* SD0_WP */
-                     |IPSR_24_FUNC(0)  /* SD0_CD */
-                     |IPSR_20_FUNC(0)  /* SD3_DS */
-                     |IPSR_16_FUNC(0)  /* SD3_DAT7 */
-                     |IPSR_12_FUNC(0)  /* SD3_DAT6 */
-                     |IPSR_8_FUNC(0)   /* SD3_DAT5 */
-                     |IPSR_4_FUNC(0)   /* SD3_DAT4 */
-                     |IPSR_0_FUNC(0)); /* SD3_DAT3 */
+                     | IPSR_24_FUNC(0) /* SD0_CD */
+                     | IPSR_20_FUNC(0) /* SD3_DS */
+                     | IPSR_16_FUNC(0) /* SD3_DAT7 */
+                     | IPSR_12_FUNC(0) /* SD3_DAT6 */
+                     | IPSR_8_FUNC(0)  /* SD3_DAT5 */
+                     | IPSR_4_FUNC(0)  /* SD3_DAT4 */
+                     | IPSR_0_FUNC(0));        /* SD3_DAT3 */
        pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
                      | IPSR_24_FUNC(0)
                      | IPSR_20_FUNC(2) /* AUDIO_CLKOUT1_A */
-                     |IPSR_16_FUNC(2)  /* AUDIO_CLKOUT_A */
-                     |IPSR_12_FUNC(0)
+                     | IPSR_16_FUNC(2) /* AUDIO_CLKOUT_A */
+                     | IPSR_12_FUNC(0)
                      | IPSR_8_FUNC(0)
                      | IPSR_4_FUNC(0)  /* SD1_WP */
-                     |IPSR_0_FUNC(0)); /* SD1_CD */
+                     | IPSR_0_FUNC(0));        /* SD1_CD */
        pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
                      | IPSR_24_FUNC(0)
                      | IPSR_20_FUNC(0)
                      | IPSR_16_FUNC(0)
                      | IPSR_12_FUNC(0) /* RX2_A */
-                     |IPSR_8_FUNC(0)   /* TX2_A */
-                     |IPSR_4_FUNC(2)   /* AUDIO_CLKB_A */
-                     |IPSR_0_FUNC(0));
+                     | IPSR_8_FUNC(0)  /* TX2_A */
+                     | IPSR_4_FUNC(2)  /* AUDIO_CLKB_A */
+                     | IPSR_0_FUNC(0));
        pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(0)
                      | IPSR_24_FUNC(0)
                      | IPSR_20_FUNC(0)
                      | IPSR_16_FUNC(0)
                      | IPSR_12_FUNC(0)
                      | IPSR_8_FUNC(2)  /* AUDIO_CLKC_A */
-                     |IPSR_4_FUNC(1)   /* HTX2_A */
-                     |IPSR_0_FUNC(1)); /* HRX2_A */
+                     | IPSR_4_FUNC(1)  /* HTX2_A */
+                     | IPSR_0_FUNC(1));        /* HRX2_A */
        pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(3)       /* USB0_PWEN_B */
-                     |IPSR_24_FUNC(0)  /* SSI_SDATA4 */
-                     |IPSR_20_FUNC(0)  /* SSI_SDATA3 */
-                     |IPSR_16_FUNC(0)  /* SSI_WS349 */
-                     |IPSR_12_FUNC(0)  /* SSI_SCK349 */
-                     |IPSR_8_FUNC(0)
+                     | IPSR_24_FUNC(0) /* SSI_SDATA4 */
+                     | IPSR_20_FUNC(0) /* SSI_SDATA3 */
+                     | IPSR_16_FUNC(0) /* SSI_WS349 */
+                     | IPSR_12_FUNC(0) /* SSI_SCK349 */
+                     | IPSR_8_FUNC(0)
                      | IPSR_4_FUNC(0)  /* SSI_SDATA1 */
-                     |IPSR_0_FUNC(0)); /* SSI_SDATA0 */
+                     | IPSR_0_FUNC(0));        /* SSI_SDATA0 */
        pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)       /* USB30_OVC */
-                     |IPSR_24_FUNC(0)  /* USB30_PWEN */
-                     |IPSR_20_FUNC(0)  /* AUDIO_CLKA */
-                     |IPSR_16_FUNC(1)  /* HRTS2#_A */
-                     |IPSR_12_FUNC(1)  /* HCTS2#_A */
-                     |IPSR_8_FUNC(0)
+                     | IPSR_24_FUNC(0) /* USB30_PWEN */
+                     | IPSR_20_FUNC(0) /* AUDIO_CLKA */
+                     | IPSR_16_FUNC(1) /* HRTS2#_A */
+                     | IPSR_12_FUNC(1) /* HCTS2#_A */
+                     | IPSR_8_FUNC(0)
                      | IPSR_4_FUNC(0)
                      | IPSR_0_FUNC(3));        /* USB0_OVC_B */
 
@@ -648,7 +651,11 @@ void pfc_init_e3(void)
                      | GPSR0_D8
                      | GPSR0_D7
                      | GPSR0_D6
-                     | GPSR0_D5 | GPSR0_D3 | GPSR0_D2 | GPSR0_D1 | GPSR0_D0);
+                     | GPSR0_D5
+                     | GPSR0_D3
+                     | GPSR0_D2
+                     | GPSR0_D1
+                     | GPSR0_D0);
        pfc_reg_write(PFC_GPSR1, GPSR1_WE0
                      | GPSR1_CS0
                      | GPSR1_A19
@@ -663,7 +670,11 @@ void pfc_init_e3(void)
                      | GPSR1_A10
                      | GPSR1_A9
                      | GPSR1_A8
-                     | GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
+                     | GPSR1_A4
+                     | GPSR1_A3
+                     | GPSR1_A2
+                     | GPSR1_A1
+                     | GPSR1_A0);
        pfc_reg_write(PFC_GPSR2, GPSR2_BIT27_REVERCED
                      | GPSR2_BIT26_REVERCED
                      | GPSR2_RD
@@ -687,7 +698,8 @@ void pfc_init_e3(void)
                      | GPSR2_QSPI0_IO3
                      | GPSR2_QSPI0_IO2
                      | GPSR2_QSPI0_MISO_IO1
-                     | GPSR2_QSPI0_MOSI_IO0 | GPSR2_QSPI0_SPCLK);
+                     | GPSR2_QSPI0_MOSI_IO0
+                     | GPSR2_QSPI0_SPCLK);
        pfc_reg_write(PFC_GPSR3, GPSR3_SD1_WP
                      | GPSR3_SD1_CD
                      | GPSR3_SD0_WP
@@ -701,7 +713,9 @@ void pfc_init_e3(void)
                      | GPSR3_SD0_DAT3
                      | GPSR3_SD0_DAT2
                      | GPSR3_SD0_DAT1
-                     | GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
+                     | GPSR3_SD0_DAT0
+                     | GPSR3_SD0_CMD
+                     | GPSR3_SD0_CLK);
        pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DS
                      | GPSR4_SD3_DAT7
                      | GPSR4_SD3_DAT6
@@ -710,13 +724,17 @@ void pfc_init_e3(void)
                      | GPSR4_SD3_DAT3
                      | GPSR4_SD3_DAT2
                      | GPSR4_SD3_DAT1
-                     | GPSR4_SD3_DAT0 | GPSR4_SD3_CMD | GPSR4_SD3_CLK);
+                     | GPSR4_SD3_DAT0
+                     | GPSR4_SD3_CMD
+                     | GPSR4_SD3_CLK);
        pfc_reg_write(PFC_GPSR5, GPSR5_SSI_SDATA9
                      | GPSR5_MSIOF0_SS2
                      | GPSR5_MSIOF0_SS1
                      | GPSR5_RX2_A
                      | GPSR5_TX2_A
-                     | GPSR5_SCK2_A | GPSR5_RTS0_TANS_A | GPSR5_CTS0_A);
+                     | GPSR5_SCK2_A
+                     | GPSR5_RTS0_TANS_A
+                     | GPSR5_CTS0_A);
        pfc_reg_write(PFC_GPSR6, GPSR6_USB30_PWEN
                      | GPSR6_SSI_SDATA6
                      | GPSR6_SSI_WS6
@@ -730,7 +748,8 @@ void pfc_init_e3(void)
                      | GPSR6_SSI_SCK349
                      | GPSR6_SSI_SDATA1
                      | GPSR6_SSI_SDATA0
-                     | GPSR6_SSI_WS01239 | GPSR6_SSI_SCK01239);
+                     | GPSR6_SSI_WS01239
+                     | GPSR6_SSI_SCK01239);
 
        /* initialize POC control */
        reg = mmio_read_32(PFC_IOCTRL30);
@@ -743,7 +762,9 @@ void pfc_init_e3(void)
               | POC_SD0_DAT3_33V
               | POC_SD0_DAT2_33V
               | POC_SD0_DAT1_33V
-              | POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
+              | POC_SD0_DAT0_33V
+              | POC_SD0_CMD_33V
+              | POC_SD0_CLK_33V);
        pfc_reg_write(PFC_IOCTRL30, reg);
        reg = mmio_read_32(PFC_IOCTRL32);
        reg = (reg & IOCTRL32_MASK);

diff --git a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
index f31d99e5696e2c02f2bc245ffd980571be1109bf..2f62bb2901d0b436bde0aa3f7ead0494cc2e8c0a 100644 (file)
--- a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+++ b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
@@ -802,7 +802,9 @@ void pfc_init_h3_v1(void)
                      | MOD_SEL0_DRIF2_A
                      | MOD_SEL0_DRIF1_A
                      | MOD_SEL0_DRIF0_A
-                     | MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A | MOD_SEL0_5LINE_A);
+                     | MOD_SEL0_CANFD0_A
+                     | MOD_SEL0_ADG_A
+                     | MOD_SEL0_5LINE_A);
        pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
                      | MOD_SEL1_TSIF0_A
                      | MOD_SEL1_TIMER_TMU_A
@@ -822,9 +824,13 @@ void pfc_init_h3_v1(void)
                      | MOD_SEL1_PWM6_A
                      | MOD_SEL1_PWM5_A
                      | MOD_SEL1_PWM4_A
-                     | MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
+                     | MOD_SEL1_PWM3_A
+                     | MOD_SEL1_PWM2_A
+                     | MOD_SEL1_PWM1_A);
        pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
-                     | MOD_SEL2_I2C_3_A | MOD_SEL2_I2C_0_A | MOD_SEL2_VIN4_A);
+                     | MOD_SEL2_I2C_3_A
+                     | MOD_SEL2_I2C_0_A
+                     | MOD_SEL2_VIN4_A);
 
        /* initialize peripheral function select */
        pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
@@ -971,7 +977,10 @@ void pfc_init_h3_v1(void)
                      | GPSR0_D14
                      | GPSR0_D13
                      | GPSR0_D12
-                     | GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
+                     | GPSR0_D11
+                     | GPSR0_D10
+                     | GPSR0_D9
+                     | GPSR0_D8);
        pfc_reg_write(PFC_GPSR1, GPSR1_EX_WAIT0_A
                      | GPSR1_A19
                      | GPSR1_A18
@@ -984,7 +993,11 @@ void pfc_init_h3_v1(void)
                      | GPSR1_A7
                      | GPSR1_A6
                      | GPSR1_A5
-                     | GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
+                     | GPSR1_A4
+                     | GPSR1_A3
+                     | GPSR1_A2
+                     | GPSR1_A1
+                     | GPSR1_A0);
        pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
                      | GPSR2_AVB_AVTP_MATCH_A
                      | GPSR2_AVB_LINK
@@ -994,7 +1007,10 @@ void pfc_init_h3_v1(void)
                      | GPSR2_PWM1_A
                      | GPSR2_IRQ5
                      | GPSR2_IRQ4
-                     | GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
+                     | GPSR2_IRQ3
+                     | GPSR2_IRQ2
+                     | GPSR2_IRQ1
+                     | GPSR2_IRQ0);
        pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
                      | GPSR3_SD0_CD
                      | GPSR3_SD1_DAT3
@@ -1004,7 +1020,9 @@ void pfc_init_h3_v1(void)
                      | GPSR3_SD0_DAT3
                      | GPSR3_SD0_DAT2
                      | GPSR3_SD0_DAT1
-                     | GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
+                     | GPSR3_SD0_DAT0
+                     | GPSR3_SD0_CMD
+                     | GPSR3_SD0_CLK);
        pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
                      | GPSR4_SD3_DAT6
                      | GPSR4_SD3_DAT3
@@ -1017,7 +1035,9 @@ void pfc_init_h3_v1(void)
                      | GPSR4_SD2_DAT3
                      | GPSR4_SD2_DAT2
                      | GPSR4_SD2_DAT1
-                     | GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
+                     | GPSR4_SD2_DAT0
+                     | GPSR4_SD2_CMD
+                     | GPSR4_SD2_CLK);
        pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
                      | GPSR5_MSIOF0_SS1
                      | GPSR5_MSIOF0_SYNC
@@ -1032,7 +1052,9 @@ void pfc_init_h3_v1(void)
                      | GPSR5_RTS1_TANS
                      | GPSR5_CTS1
                      | GPSR5_TX1_A
-                     | GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
+                     | GPSR5_RX1_A
+                     | GPSR5_RTS0_TANS
+                     | GPSR5_SCK0);
        pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
                      | GPSR6_USB30_PWEN
                      | GPSR6_USB1_OVC
@@ -1052,9 +1074,12 @@ void pfc_init_h3_v1(void)
                      | GPSR6_SSI_SCK4
                      | GPSR6_SSI_SDATA1_A
                      | GPSR6_SSI_SDATA0
-                     | GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
+                     | GPSR6_SSI_WS0129
+                     | GPSR6_SSI_SCK0129);
        pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
-                     | GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
+                     | GPSR7_HDMI0_CEC
+                     | GPSR7_AVS2
+                     | GPSR7_AVS1);
 
        /* initialize POC control register */
        pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
@@ -1071,7 +1096,9 @@ void pfc_init_h3_v1(void)
                      | POC_SD0_DAT3_33V
                      | POC_SD0_DAT2_33V
                      | POC_SD0_DAT1_33V
-                     | POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
+                     | POC_SD0_DAT0_33V
+                     | POC_SD0_CMD_33V
+                     | POC_SD0_CLK_33V);
 
        /* initialize DRV control register */
        reg = mmio_read_32(PFC_DRVCTRL0);

diff --git a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
index e53235a20edb14d842e482f3524554a3c5d4657f..116fd82ca1fe61ac332c68d1f9dd065fc306e49d 100644 (file)
--- a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+++ b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
@@ -833,7 +833,8 @@ void pfc_init_h3_v2(void)
                      | MOD_SEL0_DRIF2_A
                      | MOD_SEL0_DRIF1_A
                      | MOD_SEL0_DRIF0_A
-                     | MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A_A);
+                     | MOD_SEL0_CANFD0_A
+                     | MOD_SEL0_ADG_A_A);
        pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
                      | MOD_SEL1_TSIF0_A
                      | MOD_SEL1_TIMER_TMU_A
@@ -853,7 +854,9 @@ void pfc_init_h3_v2(void)
                      | MOD_SEL1_PWM6_A
                      | MOD_SEL1_PWM5_A
                      | MOD_SEL1_PWM4_A
-                     | MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
+                     | MOD_SEL1_PWM3_A
+                     | MOD_SEL1_PWM2_A
+                     | MOD_SEL1_PWM1_A);
        pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
                      | MOD_SEL2_I2C_3_A
                      | MOD_SEL2_I2C_0_A
@@ -864,7 +867,9 @@ void pfc_init_h3_v2(void)
                      | MOD_SEL2_SSI2_A
                      | MOD_SEL2_SSI9_A
                      | MOD_SEL2_TIMER_TMU2_A
-                     | MOD_SEL2_ADG_B_A | MOD_SEL2_ADG_C_A | MOD_SEL2_VIN4_A);
+                     | MOD_SEL2_ADG_B_A
+                     | MOD_SEL2_ADG_C_A
+                     | MOD_SEL2_VIN4_A);
 
        /* initialize peripheral function select */
        pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
@@ -1019,7 +1024,10 @@ void pfc_init_h3_v2(void)
                      | GPSR0_D14
                      | GPSR0_D13
                      | GPSR0_D12
-                     | GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
+                     | GPSR0_D11
+                     | GPSR0_D10
+                     | GPSR0_D9
+                     | GPSR0_D8);
        pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
                      | GPSR1_EX_WAIT0_A
                      | GPSR1_A19
@@ -1033,7 +1041,11 @@ void pfc_init_h3_v2(void)
                      | GPSR1_A7
                      | GPSR1_A6
                      | GPSR1_A5
-                     | GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
+                     | GPSR1_A4
+                     | GPSR1_A3
+                     | GPSR1_A2
+                     | GPSR1_A1
+                     | GPSR1_A0);
        pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
                      | GPSR2_AVB_AVTP_MATCH_A
                      | GPSR2_AVB_LINK
@@ -1043,7 +1055,10 @@ void pfc_init_h3_v2(void)
                      | GPSR2_PWM1_A
                      | GPSR2_IRQ5
                      | GPSR2_IRQ4
-                     | GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
+                     | GPSR2_IRQ3
+                     | GPSR2_IRQ2
+                     | GPSR2_IRQ1
+                     | GPSR2_IRQ0);
        pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
                      | GPSR3_SD0_CD
                      | GPSR3_SD1_DAT3
@@ -1053,7 +1068,9 @@ void pfc_init_h3_v2(void)
                      | GPSR3_SD0_DAT3
                      | GPSR3_SD0_DAT2
                      | GPSR3_SD0_DAT1
-                     | GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
+                     | GPSR3_SD0_DAT0
+                     | GPSR3_SD0_CMD
+                     | GPSR3_SD0_CLK);
        pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
                      | GPSR4_SD3_DAT6
                      | GPSR4_SD3_DAT3
@@ -1066,7 +1083,9 @@ void pfc_init_h3_v2(void)
                      | GPSR4_SD2_DAT3
                      | GPSR4_SD2_DAT2
                      | GPSR4_SD2_DAT1
-                     | GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
+                     | GPSR4_SD2_DAT0
+                     | GPSR4_SD2_CMD
+                     | GPSR4_SD2_CLK);
        pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
                      | GPSR5_MSIOF0_SS1
                      | GPSR5_MSIOF0_SYNC
@@ -1081,7 +1100,9 @@ void pfc_init_h3_v2(void)
                      | GPSR5_RTS1_TANS
                      | GPSR5_CTS1
                      | GPSR5_TX1_A
-                     | GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
+                     | GPSR5_RX1_A
+                     | GPSR5_RTS0_TANS
+                     | GPSR5_SCK0);
        pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
                      | GPSR6_USB30_PWEN
                      | GPSR6_USB1_OVC
@@ -1101,9 +1122,12 @@ void pfc_init_h3_v2(void)
                      | GPSR6_SSI_SCK4
                      | GPSR6_SSI_SDATA1_A
                      | GPSR6_SSI_SDATA0
-                     | GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
+                     | GPSR6_SSI_WS0129
+                     | GPSR6_SSI_SCK0129);
        pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
-                     | GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
+                     | GPSR7_HDMI0_CEC
+                     | GPSR7_AVS2
+                     | GPSR7_AVS1);
 
        /* initialize POC control register */
        pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
@@ -1120,7 +1144,9 @@ void pfc_init_h3_v2(void)
                      | POC_SD0_DAT3_33V
                      | POC_SD0_DAT2_33V
                      | POC_SD0_DAT1_33V
-                     | POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
+                     | POC_SD0_DAT0_33V
+                     | POC_SD0_CMD_33V
+                     | POC_SD0_CLK_33V);
 
        /* initialize DRV control register */
        reg = mmio_read_32(PFC_DRVCTRL0);

diff --git a/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c b/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
index f7e66f24585ef46e34a9e08d306e7d13d08485f1..fc12cd6eddfb93ebda571093675902429865e901 100644 (file)
--- a/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
+++ b/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
@@ -867,7 +867,9 @@ static void StartRtDma0_Descriptor(void)
                /* Set transfer parameter, Start transfer */
                mmio_write_32(RTDMAC_RDMCHCR(RTDMAC_CH), RDMCHCR_DPM_INFINITE
                              | RDMCHCR_RPT_TCR
-                             | RDMCHCR_TS_2 | RDMCHCR_RS_AUTO | RDMCHCR_DE);
+                             | RDMCHCR_TS_2
+                             | RDMCHCR_RS_AUTO
+                             | RDMCHCR_DE);
        }
 }
 
@@ -913,7 +915,8 @@ void pfc_init_m3(void)
                      | MOD_SEL0_DRIF2_A
                      | MOD_SEL0_DRIF1_A
                      | MOD_SEL0_DRIF0_A
-                     | MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A_A);
+                     | MOD_SEL0_CANFD0_A
+                     | MOD_SEL0_ADG_A_A);
        pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
                      | MOD_SEL1_TSIF0_A
                      | MOD_SEL1_TIMER_TMU_A
@@ -933,7 +936,9 @@ void pfc_init_m3(void)
                      | MOD_SEL1_PWM6_A
                      | MOD_SEL1_PWM5_A
                      | MOD_SEL1_PWM4_A
-                     | MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
+                     | MOD_SEL1_PWM3_A
+                     | MOD_SEL1_PWM2_A
+                     | MOD_SEL1_PWM1_A);
        pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
                      | MOD_SEL2_I2C_3_A
                      | MOD_SEL2_I2C_0_A
@@ -944,7 +949,9 @@ void pfc_init_m3(void)
                      | MOD_SEL2_SSI2_A
                      | MOD_SEL2_SSI9_A
                      | MOD_SEL2_TIMER_TMU2_A
-                     | MOD_SEL2_ADG_B_A | MOD_SEL2_ADG_C_A | MOD_SEL2_VIN4_A);
+                     | MOD_SEL2_ADG_B_A
+                     | MOD_SEL2_ADG_C_A
+                     | MOD_SEL2_VIN4_A);
 
        /* initialize peripheral function select */
        pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
@@ -1099,7 +1106,10 @@ void pfc_init_m3(void)
                      | GPSR0_D14
                      | GPSR0_D13
                      | GPSR0_D12
-                     | GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
+                     | GPSR0_D11
+                     | GPSR0_D10
+                     | GPSR0_D9
+                     | GPSR0_D8);
        pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
                      | GPSR1_EX_WAIT0_A
                      | GPSR1_A19
@@ -1113,7 +1123,11 @@ void pfc_init_m3(void)
                      | GPSR1_A7
                      | GPSR1_A6
                      | GPSR1_A5
-                     | GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
+                     | GPSR1_A4
+                     | GPSR1_A3
+                     | GPSR1_A2
+                     | GPSR1_A1
+                     | GPSR1_A0);
        pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
                      | GPSR2_AVB_AVTP_MATCH_A
                      | GPSR2_AVB_LINK
@@ -1123,7 +1137,10 @@ void pfc_init_m3(void)
                      | GPSR2_PWM1_A
                      | GPSR2_IRQ5
                      | GPSR2_IRQ4
-                     | GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
+                     | GPSR2_IRQ3
+                     | GPSR2_IRQ2
+                     | GPSR2_IRQ1
+                     | GPSR2_IRQ0);
        pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
                      | GPSR3_SD0_CD
                      | GPSR3_SD1_DAT3
@@ -1133,7 +1150,9 @@ void pfc_init_m3(void)
                      | GPSR3_SD0_DAT3
                      | GPSR3_SD0_DAT2
                      | GPSR3_SD0_DAT1
-                     | GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
+                     | GPSR3_SD0_DAT0
+                     | GPSR3_SD0_CMD
+                     | GPSR3_SD0_CLK);
        pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
                      | GPSR4_SD3_DAT6
                      | GPSR4_SD3_DAT3
@@ -1146,7 +1165,9 @@ void pfc_init_m3(void)
                      | GPSR4_SD2_DAT3
                      | GPSR4_SD2_DAT2
                      | GPSR4_SD2_DAT1
-                     | GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
+                     | GPSR4_SD2_DAT0
+                     | GPSR4_SD2_CMD
+                     | GPSR4_SD2_CLK);
        pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
                      | GPSR5_MSIOF0_SS1
                      | GPSR5_MSIOF0_SYNC
@@ -1161,7 +1182,9 @@ void pfc_init_m3(void)
                      | GPSR5_RTS1_TANS
                      | GPSR5_CTS1
                      | GPSR5_TX1_A
-                     | GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
+                     | GPSR5_RX1_A
+                     | GPSR5_RTS0_TANS
+                     | GPSR5_SCK0);
        pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
                      | GPSR6_USB30_PWEN
                      | GPSR6_USB1_OVC
@@ -1181,9 +1204,12 @@ void pfc_init_m3(void)
                      | GPSR6_SSI_SCK4
                      | GPSR6_SSI_SDATA1_A
                      | GPSR6_SSI_SDATA0
-                     | GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
+                     | GPSR6_SSI_WS0129
+                     | GPSR6_SSI_SCK0129);
        pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
-                     | GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
+                     | GPSR7_HDMI0_CEC
+                     | GPSR7_AVS2
+                     | GPSR7_AVS1);
 
        /* initialize POC control register */
        pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
@@ -1200,7 +1226,9 @@ void pfc_init_m3(void)
                      | POC_SD0_DAT3_33V
                      | POC_SD0_DAT2_33V
                      | POC_SD0_DAT1_33V
-                     | POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
+                     | POC_SD0_DAT0_33V
+                     | POC_SD0_CMD_33V
+                     | POC_SD0_CLK_33V);
 
        /* initialize DRV control register */
        reg = mmio_read_32(PFC_DRVCTRL0);

diff --git a/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c b/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
index e6b8a4f2842e9cb8be3d37e7fafe890efb9b40c4..07f08fa0dda5e07193a782d433f6c592dc6d5d1d 100644 (file)
--- a/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
+++ b/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
@@ -821,7 +821,8 @@ void pfc_init_m3n(void)
                      | MOD_SEL0_DRIF2_A
                      | MOD_SEL0_DRIF1_A
                      | MOD_SEL0_DRIF0_A
-                     | MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A_A);
+                     | MOD_SEL0_CANFD0_A
+                     | MOD_SEL0_ADG_A_A);
        pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
                      | MOD_SEL1_TSIF0_A
                      | MOD_SEL1_TIMER_TMU_A
@@ -841,7 +842,9 @@ void pfc_init_m3n(void)
                      | MOD_SEL1_PWM6_A
                      | MOD_SEL1_PWM5_A
                      | MOD_SEL1_PWM4_A
-                     | MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
+                     | MOD_SEL1_PWM3_A
+                     | MOD_SEL1_PWM2_A
+                     | MOD_SEL1_PWM1_A);
        pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
                      | MOD_SEL2_I2C_3_A
                      | MOD_SEL2_I2C_0_A
@@ -852,7 +855,9 @@ void pfc_init_m3n(void)
                      | MOD_SEL2_SSI2_A
                      | MOD_SEL2_SSI9_A
                      | MOD_SEL2_TIMER_TMU2_A
-                     | MOD_SEL2_ADG_B_A | MOD_SEL2_ADG_C_A | MOD_SEL2_VIN4_A);
+                     | MOD_SEL2_ADG_B_A
+                     | MOD_SEL2_ADG_C_A
+                     | MOD_SEL2_VIN4_A);
 
        /* initialize peripheral function select */
        pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
@@ -1007,7 +1012,10 @@ void pfc_init_m3n(void)
                      | GPSR0_D14
                      | GPSR0_D13
                      | GPSR0_D12
-                     | GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
+                     | GPSR0_D11
+                     | GPSR0_D10
+                     | GPSR0_D9
+                     | GPSR0_D8);
        pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
                      | GPSR1_EX_WAIT0_A
                      | GPSR1_A19
@@ -1021,7 +1029,11 @@ void pfc_init_m3n(void)
                      | GPSR1_A7
                      | GPSR1_A6
                      | GPSR1_A5
-                     | GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
+                     | GPSR1_A4
+                     | GPSR1_A3
+                     | GPSR1_A2
+                     | GPSR1_A1
+                     | GPSR1_A0);
        pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
                      | GPSR2_AVB_AVTP_MATCH_A
                      | GPSR2_AVB_LINK
@@ -1031,7 +1043,10 @@ void pfc_init_m3n(void)
                      | GPSR2_PWM1_A
                      | GPSR2_IRQ5
                      | GPSR2_IRQ4
-                     | GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
+                     | GPSR2_IRQ3
+                     | GPSR2_IRQ2
+                     | GPSR2_IRQ1
+                     | GPSR2_IRQ0);
        pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
                      | GPSR3_SD0_CD
                      | GPSR3_SD1_DAT3
@@ -1041,7 +1056,9 @@ void pfc_init_m3n(void)
                      | GPSR3_SD0_DAT3
                      | GPSR3_SD0_DAT2
                      | GPSR3_SD0_DAT1
-                     | GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
+                     | GPSR3_SD0_DAT0
+                     | GPSR3_SD0_CMD
+                     | GPSR3_SD0_CLK);
        pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
                      | GPSR4_SD3_DAT6
                      | GPSR4_SD3_DAT3
@@ -1054,7 +1071,9 @@ void pfc_init_m3n(void)
                      | GPSR4_SD2_DAT3
                      | GPSR4_SD2_DAT2
                      | GPSR4_SD2_DAT1
-                     | GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
+                     | GPSR4_SD2_DAT0
+                     | GPSR4_SD2_CMD
+                     | GPSR4_SD2_CLK);
        pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
                      | GPSR5_MSIOF0_SS1
                      | GPSR5_MSIOF0_SYNC
@@ -1069,7 +1088,9 @@ void pfc_init_m3n(void)
                      | GPSR5_RTS1_TANS
                      | GPSR5_CTS1
                      | GPSR5_TX1_A
-                     | GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
+                     | GPSR5_RX1_A
+                     | GPSR5_RTS0_TANS
+                     | GPSR5_SCK0);
        pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
                      | GPSR6_USB30_PWEN
                      | GPSR6_USB1_OVC
@@ -1089,9 +1110,12 @@ void pfc_init_m3n(void)
                      | GPSR6_SSI_SCK4
                      | GPSR6_SSI_SDATA1_A
                      | GPSR6_SSI_SDATA0
-                     | GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
+                     | GPSR6_SSI_WS0129
+                     | GPSR6_SSI_SCK0129);
        pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
-                     | GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
+                     | GPSR7_HDMI0_CEC
+                     | GPSR7_AVS2
+                     | GPSR7_AVS1);
 
        /* initialize POC control register */
        pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
@@ -1108,7 +1132,9 @@ void pfc_init_m3n(void)
                      | POC_SD0_DAT3_33V
                      | POC_SD0_DAT2_33V
                      | POC_SD0_DAT1_33V
-                     | POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
+                     | POC_SD0_DAT0_33V
+                     | POC_SD0_CMD_33V
+                     | POC_SD0_CLK_33V);
 
        /* initialize DRV control register */
        reg = mmio_read_32(PFC_DRVCTRL0);